This invention relates to a charge-coupled device which is particularly suited for use as an output stage of a serial-parallel-serial (SPS) charge-coupled device memory.
An SPS memory has series input and output registers each consisting of a charge conduction channel across which extends, alternately, charge storage and charge transfer electrodes for enabling charge packets to be transported along the channel. Between the series registers is provided a parallel section or register which has a number of parallel channels across which extend alternate charge storage and charge transfer electrodes. Each charge storage electrode of the parallel register is arranged to define with the underlying channels a row of charge storage sites for storing information transferred to the parallel register from the series input register. As alternate charge storage sites of the series registers are empty when a row of information has been input to the series register, a technique called "interlacing" is used to enable full use of the storage space in the parallel register. Thus, after one subsidiary row of information has been transferred to the parallel register from the series register so that only alternate charge storage sites of the first row of the parallel register are occupied another subsidiary row of information is input to the series input register and then transferred to the parallel register so as to occupy the remaining charge storage sites of the first row. Thus the two subsidiary rows of information are interlaced.
In order that the information be output in the same order in which it was input to the memory, a technique for de-interlacing the interlaced subsidiary rows is required so that the one subsidiary row can be output via the output series register followed by the other subsidiary row.
U.S. application Ser. No. 3967254 describes such a technique for effecting de-interlacing in which the parallel register has an output stage or structure consisting of first and second charge storage electrodes having respectively first and second rows of teeth which are interdigitated so that the teeth of the first row lie over respective ones of the one subsidiary group of channels and the teeth of the second row lie over respective ones of the other subsidiary group of channels.
A first charge transfer electrode of the output stage is provided to transfer a row of information from the row of charge storage sites beneath the preceding charge storage electrode of the parallel section into a row of charge storage sites beneath the first charge storage electrode. A second charge transfer electrode is provided for transferring charge packets between charge storage sites beneath portions of the first charge storage electrode between the first row of teeth and charge storage sites beneath the second row of teeth while a third charge transfer electrode is provided for transferring charge packets between charge storage sites beneath the first row of teeth and the portions of the second charge storage electrode between the teeth of the second row.
By supplying appropriate clock signals to clock lines controlling the first and second charge storage electrodes the subsidiary rows of information can be separated so that, for example, the subsidiary row of information stored at charge storage sites beneath the teeth of the first row can be transferred to charge storage sites beneath the second charge storage electrode and then output via a transfer gate and series output register while the other subsidiary row remains stored at charge storage sites under the intervening portions of the first charge storage electrode to be output subsequently.
Although the output stage described in U.S. application Ser. No. 3967254 enables the required separation of subsidiary rows of information where a drop-clock scheme of clocking pulses is used, if it is desired to use a push-clock scheme of clocking pulses the output stage described in U.S. application Ser. No. 3967254 is not acceptable because it would be impossible to apply a clocking signal to the first charge storage electrode of the output stage which would cause charge packets stored under, for example, the teeth of the first row to be pushed (with the appropriate clock signal applied to the third charge transfer electrode), into potential wells formed at charge storage sites beneath the second charge storage electrode while still maintaining potential wells for the remaining subsidiary row of information at charge storage sites beneath the intervening portions of the first charge storage electrode.